This application is based on and claims the benefit of priority from prior Japanese Patent Applications No. 2001-225027, filed on Jul. 25, 2001 and No. 2001-229409, filed Jul. 30, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates generally to semiconductor devices with a plurality of types of transistors integrated together and, more particularly, to methodology of fabricating a semiconductor device including an array of non-volatile memory cells formed of transistors, also known as xe2x80x9cmemory transistors.xe2x80x9d
2. Description of the Related Art
Nonvolatile semiconductor memory devices including but not limited to xe2x80x9cflashxe2x80x9d electrically erasable programmable read only memory (EEPROM) chips of the NAND cell type are typically designed to employ memory transistors with metal insulator semiconductor field effect transistor (MISFET) structures. These memory transistors each have a lamination or multilayer structure of an electrically isolated gate, typically termed xe2x80x9cfloatingxe2x80x9d gate, for use as a charge storage layer and a control gate over a semiconductive chip substrate. A dielectric insulating film for use as a gate insulator (gate insulator film) is interposed between the floating gate and the substrate. This gate insulator film is formed of a tunnel dielectric film with a thickness of approximately 8 nanometers (nm) in light of carrier injection and release (charge and discharge) between the substrate and the floating gate and also the data retaining characteristics required.
On the other hand, peripheral circuitry for performing data write/erase/read control of a cell array includes high voltage-driven transistors to which a potentially increased or xe2x80x9craisedxe2x80x9d voltage directly relating to write and erase operations is given and low voltage-driven transistors operable with a power supply voltage. The high voltage transistors make use of a gate insulator film as thin as about 35 nm to provide enhanced durability against high voltages applied thereto. The low voltage transistors use a thinner gate insulator film.
These three kinds of gate insulator filmsxe2x80x94that is, the tunnel dielectric, high voltage transistor gate insulator, and low voltage transistor gate insulator filmsxe2x80x94are obtainable for example by a process which follows. Firstly, form by thermal oxidation a gate oxide film with a thickness of 3 nm in a cell array region of a silicon substrate. Then, let the substrate surface be exposed at its selected portion in a high voltage transistor region. Next, perform thermal oxidation again to thereby form a gate oxide film which is about 30 nm thick. Subsequently, expose a surface portion of the substrate in a low voltage transistor region and then perform thermal oxidation, thereby forming a gate oxide film of about 5 nm thickness. Through repeated effectuation of thermal oxidation processes, a gate oxide film of about 8 nm thick is finally obtained in the cell array region, with a gate oxide film of about 35 nm thick being formed in the high voltage transistor region.
However, such method for sequentially forming the gate oxide films in the respective circuit regions is under strict and severe requirements for film thickness controllability. In particular, the tunnel dielectric film for use in memory transistors is sensitive to even a small mount of slight film thickness variation in view of the fact that this film directly affects the data write/erase/retain characteristics. This makes it difficult to obtain higher production yields and increased reliability.
Additionally, it is also important for the memory transistor tunnel dielectric film to offer superior film quality other than the accurate thickness controllability. It has been traditionally known among those skilled in the semiconductor device art that film quality degradation occurs due to some causes, one of which is contamination from resist masks. With the method having the steps of forming an oxide film for later use as the tunnel dielectric film of the cell array region, directly forming on its surface a resist mask, and then etching a portion of the tunnel dielectric film of peripheral circuitry to thereby expose its corresponding substrate surface, it is impossible to obtain any intended tunnel dielectric film of high quality.
Methods for precluding resist contamination of the tunnel dielectric film of the cell array have been proposed until today, one of which is disclosed, for example, in Japanese Patent Publication (Kokoku) No. 8-21636. With this method as taught thereby, immediately after having formed a desired tunnel dielectric film in the cell array region, deposit thereon a polycrystalline silicon or xe2x80x9cpoly-siliconxe2x80x9d film for later use as portions of gate electrodes. Then, form a resist mask pattern having an opening in a peripheral circuit region. Next, remove by etching the polysilicon film and its underlying gate insulator film, thus forming a gate insulator film of the peripheral circuitry.
If the gate insulator films for use in high-voltage and low-voltage transistors of the peripheral circuitry are formed sequentially while letting the cell array region""s tunnel dielectric film be covered with the polysilicon film in this way, then the tunnel dielectric is no longer contaminated while guaranteeing that no appreciable film thickness changes take place even during thermal oxidation processes to be later performed. This enables achievement of good thickness controllability and improved film quality.
Unfortunately, even the method of making the gate insulator film of peripheral circuitry while letting the tunnel dielectric film be covered or coated with the polysilicon film is encountered with problems that follow. A first problem is that even in the state that a polysilicon film is formed for use as part of floating gates, memory transistors can decrease in reliability if its following thermal processing is done at high temperatures for an increased length of time period. FIG. 20 shows a typical pattern of threshold voltage variation or change as measured when a memory transistor is repeatedly subject to write and erase cycles.
As shown in FIG. 20, in regard to both the write state (i.e. electron is injected to a floating gate resulting in a threshold voltage being made higher) and the erase state (the stored electron is released out of the floating gate resulting in the threshold voltage being lowered), the threshold voltage tends to potentially rise up with an increase in write/erase cycle number. When compared to the case (indicated by solid lines in FIG. 20) where thermal processing after floating gate formation is carried out at relatively low temperatures for a shortened time period, the tendency becomes more significant when the thermal process is done at higher temperature for a longer time period (indicated by dotted lines). As a example, successful fabrication of a 30-nm thick gate insulator film for use in high voltage transistors requires thermal oxidation at 1150xc2x0 C. for 200 seconds, or more or less. This would result in a decrease in reliability of the memory transistors which are covered by the polysilicon film.
A second problem faced with the above-noted prior known method lies in occurrence of re-diffusion of doped impurity due to thermal processing. More specifically, when doping impurity ions into the cell array region for transistor threshold voltage adjustment purposes prior to formation of the gate insulator film of the peripheral circuitry, in particular, during the high-temperature/long-time thermal oxidation process for forming the gate oxide film of high voltage transistors, rediffusion of doped impurity can take place. This disables achievement of any desired impurity concentration profile in the cell array region. Especially in the cell array with a layout of micropatterned ultra-fine memory transistors, it is desired to accurately control the carrier concentration profile of an impurity doped in transistor channel in order to reduce the so-called xe2x80x9cshort channelxe2x80x9d effects and back-bias effects.
Another problem faced with the EEPROM fabrication process is as follows. Currently available NAND-EEPROM fabrication processes include the one which has the steps of (i) burying and forming an element isolating dielectric film by using shallow trench isolation (STI) technologies after having formed a first gate electrode martial film for later use as part of floating gates of memory transistors and also as part of gates of peripheral circuit transistors, (ii) depositing a second gate electrode material film on the first gate electrode material film, (iii) forming slits in the second gate electrode material film in a cell array region, each of which is for separation between the floating gates, (iv) sequentially depositing a gate-to-gate isolation or xe2x80x9cinter-gatexe2x80x9d dielectric film and a third gate electrode material film for use as control gates of the memory transistors, and (v) selectively etching the first to third gate electrode material films to form gates of the memory transistors and of the peripheral circuit transistors.
In this process, at the element isolation step, the first gate electrode material film is covered by a stopper film, which will later be removed away after the element isolation dielectric film is buried. Due to this, the second gate electrode material film is formed in such a state that the element isolation dielectric film is projected. Recall here that the cell array region is such that the memory transistors are laid out with a greater integration density than that in the peripheral circuitry; thus, the cell array region is inherently less in width of element formation region than the peripheral circuit region. The result of this is that the third gate electrode material film is formed so that its thickness in the cell array region is greater than that in the peripheral circuit region. This is because element formation regions exhibit recess portions at ultrafine intervals or pitches in the cell array region. In this case, if, at a later process step of patterning all the gates of respective transistors at a time, any required sufficient etching time is taken for the cell array, then over-etching would occur in the peripheral circuit region. Adversely, if the sufficient etching required is done in the peripheral circuit region then etch-failed portions can occur in the cell array region. As stated previously, both the high voltage transistors having a thick gate insulator film and the low voltage transistors with a thin gate insulator film are formed in the peripheral circuitry. In particular in the region of such low voltage transistors, if the above-noted overetching is present then the substrate per se is readily etched unwantedly. This makes it difficult to obtain any low voltage transistors of excellent characteristics.
A method of fabricating a semiconductor device having a cell array with a layout of non-volatile memory transistors and a peripheral circuit including a first transistor and a second transistor driven by a lower voltage than the first transistor, includes forming over a semiconductor substrate a first gate dielectric film for use in the first transistor, selectively etching the first gate dielectric film in a region of the cell array to expose the semiconductor substrate, forming over the semiconductor substrate thus exposed a second gate dielectric film for use as a tunnel dielectric film of the memory transistors, the second gate dielectric film being thinner than the first gate dielectric film, forming a first gate electrode material film over the first and second gate dielectric films, selectively etching the first gate electrode material film and the first gate dielectric film thereunder in a region of the second transistor to expose the semiconductor substrate, forming over the semiconductor substrate thus exposed a third gate dielectric film for use in the second transistor, the third gate dielectric film being thinner than the second gate dielectric film, forming a second gate electrode material film over the third gate dielectric film, and forming gates of the first and second transistors and of the memory transistors while letting the gates at least partly include the first and second gate electrode material films.